Stirling Networks: A Versatile Combinatorial Topology for Multiprocessor Systems

We derive a family of labeled, undirected graphs from the Stirling table of the rst kind and investigate properties of these graphs as a basis for multiprocessor interconnection networks. The diameter of a Stirling network with n nodes is dlog2(n + 1)e 1, the average distance is less than 10/3, and the number of links is O(n1:59). Stirling networks can be inductively speci ed with incrementability of one, and adjacencies can be determined solely by the node addresses. Many standard networks including full-ringed binary trees, tree-machines, meshes and half mesh-of-trees are shown to be embedded in these combinatorial networks. Properties of Stirling networks are analyzed and related to the underlying mathematical structure. We present a routing scheme that is deadlock-free, avoids congestions, and can be executed on-they by bit manipulation of node labels. A methodology for modular construction of these networks yields estimates for the VLSI area required for their layout. Fault-tolerance properties are analyzed, a vulnerability of 1 is proved, and fault-handling abilities in presence of faulty nodes or links are demonstrated. We also show how several classes of parallel algorithms can be e ciently implemented using these networks. ii